The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jul. 25, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Ying-Chih Hsu, Hsinchu, TW;

Alan Roth, Leander, TX (US);

Chuei-Tang Wang, Taichung, TW;

Chih-Yuan Chang, Hsinchu, TW;

Eric Soenen, Austin, TX (US);

Chih-Lin Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 21/48 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3677 (2013.01); H01L 21/486 (2013.01); H01L 23/481 (2013.01); H01L 23/49822 (2013.01);
Abstract

A package structure includes a first package layer, a second package layer, and a chip layer positioned between the first package layer and the second package layer. The first package layer includes an electrical signal structure electrically isolated from a first thermal conduction structure. The chip layer includes an integrated circuit (IC) chip electrically connected to the electrical signal structure, a molding material, and a through-via positioned in the molding material. The first thermal conduction structure, the through-via, and the second thermal conduction structure are configured as a low thermal resistance path from the IC chip to a surface of the second package layer opposite the chip layer.


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