The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 25, 2018

Filed:

Jan. 06, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Shih-Kang Fu, Taoyuan, TW;

Ming-Han Lee, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 29/06 (2006.01); H01L 21/3105 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76883 (2013.01); H01L 21/7684 (2013.01); H01L 21/7688 (2013.01); H01L 21/76834 (2013.01); H01L 21/76879 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 29/0692 (2013.01); H01L 21/31053 (2013.01); H01L 21/3212 (2013.01); H01L 21/76885 (2013.01); H01L 23/5283 (2013.01);
Abstract

Semiconductor structures and methods for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a dielectric layer over a substrate and forming a sacrificial layer over the dielectric layer. The method for manufacturing a semiconductor structure further includes forming a trench through the sacrificial layer and the dielectric layer and forming a conductive structure in the trench. The method for manufacturing a semiconductor structure further includes removing the sacrificial layer. In addition, a top surface of the conductive feature is not level with a top surface of the dielectric layer after the sacrificial layer is removed.


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