The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Jul. 17, 2017
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Feng-Chi Hung, Chu-Bei, TW;

Jhy-Jyi Sze, Hsinchu, TW;

Shou-Gwo Wuu, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/423 (2006.01); H01L 27/146 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 21/02 (2006.01); H01L 29/417 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 21/266 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14616 (2013.01); H01L 21/0223 (2013.01); H01L 21/266 (2013.01); H01L 21/26506 (2013.01); H01L 21/26586 (2013.01); H01L 21/2822 (2013.01); H01L 21/28123 (2013.01); H01L 21/76224 (2013.01); H01L 27/1463 (2013.01); H01L 27/14603 (2013.01); H01L 27/14612 (2013.01); H01L 29/0653 (2013.01); H01L 29/41775 (2013.01); H01L 29/42368 (2013.01); H01L 29/66568 (2013.01); H01L 29/78 (2013.01);
Abstract

Semiconductor devices and methods of forming semiconductor devices are disclosed. In some embodiments, a first trench and a second trench are formed in a substrate, and dopants of a first conductivity type are implanted along sidewalls and a bottom of the first trench and the second trench. The first and second trenches are filled with an insulating material, and a gate dielectric and a gate electrode over the substrate, the gate dielectric and the gate electrode extending over the first trench and the second trench. Source/drain regions are formed in the substrate on opposing sides of the gate dielectric and the gate electrode.


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