The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 18, 2018

Filed:

Nov. 28, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Kuo-Nan Yang, Hsinchu, TW;

Chung-Hsing Wang, Baoshan Township, TW;

Yi-Kan Cheng, Taipei, TW;

Kumar Lalgudi, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/528 (2006.01); H03K 5/15 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5077 (2013.01); G06F 17/5081 (2013.01); H01L 23/528 (2013.01); H03K 5/15066 (2013.01); G06F 2217/62 (2013.01); H01L 23/5283 (2013.01);
Abstract

In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first clock line having a first line width and being arranged at a first height as measured from an upper surface of the semiconductor substrate. The clock tree structure also includes a second clock line having a second line width, which differs from the first line width. The second clock line is arranged at a second height as measured from the upper surface of the semiconductor substrate and the second height is equal to the first height. The first line width can be directly proportional to a first current level for the first clock line and the second line width can be directly proportional to a second current level for the second clock line.


Find Patent Forward Citations

Loading…