The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 11, 2018
Filed:
Oct. 26, 2017
United Microelectronics Corp., Hsin-Chu, TW;
Shu-Ru Wang, Taichung, TW;
Ching-Cheng Lung, Tainan, TW;
Yu-Tse Kuo, Tainan, TW;
Chien-Hung Chen, Taipei, TW;
Chun-Hsien Huang, Tainan, TW;
Li-Ping Huang, Miaoli County, TW;
Chun-Yen Tseng, Tainan, TW;
Meng-Ping Chuang, Hsinchu, TW;
UNITED MICROELECTRONICS CORP., Hsin-Chu, TW;
Abstract
A layout pattern of a static random access memory (SRAM) includes a substrate, a first pull-up transistor (PL), a first pull-down transistor (PD), a second (PL), and a second pull-down transistor (PD) on the substrate, and a first pass gate transistor (PGA), a second pass gate transistor (PGB), a third pass gate transistor (PGA) and a fourth pass gate transistor (PGB), wherein the PGA and the PGB comprise an identical first fin structure, the PGA and the PGB comprise an identical second fin structure, a first local interconnection layer disposed between the PGA and the PGB and disposed on the fin structures of the PLand the PD, a second local interconnection layer disposed between the PGA and the PGB and disposed between the fin structures of the PLand the PD