The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 11, 2018

Filed:

Apr. 11, 2017
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Gerald Ofner, Regensburg, DE;

Thorsten Meyer, Regensburg, DE;

Reinhard Mahnkopf, Oberhaching, DE;

Christian Geissler, Teugn, DE;

Andreas Augustin, Munich, DE;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); B81C 1/00 (2006.01); B81B 7/00 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00238 (2013.01); B81B 7/008 (2013.01); B81C 1/0023 (2013.01); B81B 2201/025 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0242 (2013.01); B81B 2201/0257 (2013.01); B81B 2201/0264 (2013.01); B81B 2201/0271 (2013.01); B81B 2201/10 (2013.01); B81B 2207/012 (2013.01); B81B 2207/053 (2013.01); B81B 2207/07 (2013.01); B81B 2207/096 (2013.01); B81C 2203/0792 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/48091 (2013.01); H01L 2924/15311 (2013.01);
Abstract

In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.


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