The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

May. 29, 2017
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Hiromasa Susuki, Yokkaichi, JP;

Masanori Tsutsumi, Yokkaichi, JP;

Shigehisa Inoue, Yokkaichi, JP;

Junji Oh, Yokkaichi, JP;

Kensuke Yamaguchi, Yokkaichi, JP;

Seiji Shimabukuro, Yokkaichi, JP;

Yuji Fukano, Yokkaichi, JP;

Ryoichi Ehara, Yokkaichi, JP;

Youko Furihata, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, the alternating stack containing a memory array region and a terrace region. Memory stack structures containing a memory film and a vertical semiconductor channel extend through the memory array region of the alternating stack. Support pillar structures extending through the terrace region of the alternating stack. The support pillar structures have different heights from each other.


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