The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 27, 2018

Filed:

Dec. 23, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Yi Peng, Taipei, TW;

Yu-Lin Yang, Hsinchu County, TW;

Chia-Cheng Ho, Hsinchu, TW;

Hung-Li Chiang, Taipei, TW;

Wei-Jen Lai, Keelung, TW;

Tzu-Chiang Chen, Hsinchu, TW;

Tsung-Lin Lee, Hsinchu, TW;

Chih Chieh Yeh, Taipei, TW;

Chih-Sheng Chang, Hsinchu, TW;

Yee-Chia Yeo, Albany, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/161 (2006.01); H01L 29/36 (2006.01); H01L 29/10 (2006.01); H01L 21/265 (2006.01); H01L 21/8238 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0921 (2013.01); H01L 21/265 (2013.01); H01L 21/82385 (2013.01); H01L 21/823456 (2013.01); H01L 21/823493 (2013.01); H01L 21/823821 (2013.01); H01L 21/823892 (2013.01); H01L 27/0922 (2013.01); H01L 27/0924 (2013.01); H01L 29/1033 (2013.01); H01L 29/1083 (2013.01); H01L 29/161 (2013.01); H01L 29/36 (2013.01); H01L 29/66795 (2013.01); H01L 21/823431 (2013.01);
Abstract

A method of fabricating a semiconductor device includes forming a plurality of isolation features on a semiconductor substrate, thereby defining a first set of semiconductor features, performing an etching process on the first set of semiconductor features such that larger semiconductor features are etched deeper than smaller semiconductor features, after the etching process, forming anti-punch-through features on surfaces of the exposed features of the first set of semiconductor features, forming a semiconductor layer over the anti-punch-through features, and forming transistors on the semiconductor layer of each of the features of the first set of semiconductor features.


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