The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 20, 2018
Filed:
Aug. 19, 2015
The Regents of the University of California, Oakland, CA (US);
Globalfoundries, Inc., Santa Clara, CA (US);
Applied Materials, Inc., Santa Clara, CA (US);
Kasra Sardashti, San Diego, CA (US);
Tobin Kaufman-Osborn, San Diego, CA (US);
Tyler Kent, San Diego, CA (US);
Andrew Kummel, San Diego, CA (US);
Shariq Siddiqui, Albany, NY (US);
Bhagawan Sahu, Albany, NY (US);
Adam Brand, Sunnyvale, CA (US);
Naomi Yoshida, Sunnyvale, CA (US);
The Regents of the University of California, Oakland, CA (US);
Abstract
Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.