IDiyas

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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 10128343 B1

PDFFull Text
Date of Patent:
Nov. 13, 2018

Filed:

Mar. 09, 2018

Iii-v mosfet with self-aligned diffusion barrier

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Kevin K. Chan, Staten Island, NY (US);

Cheng-Wei Cheng, White Plains, NY (US);

Jack Oon Chu, Manhasset Hills, NY (US);

Yanning Sun, Scarsdale, NY (US);

Jeng-Bang Yau, Yorktown Heights, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

L. Jeffrey Kelly, Esq.

Hoffmann & Baron, LLP

Primary Examiner:

Ida M Soward

Int. Cl.
CPC ...
H01L 29/41 (2006.01); H01L 29/08 (2006.01); H01L 29/20 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/417 (2006.01); H01L 21/3205 (2006.01); H01L 21/3213 (2006.01); H01L 21/283 (2006.01); H01L 29/201 (2006.01); H01L 21/285 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41783 (2013.01); H01L 21/0262 (2013.01); H01L 21/02546 (2013.01); H01L 21/02631 (2013.01); H01L 21/283 (2013.01); H01L 21/28575 (2013.01); H01L 21/32051 (2013.01); H01L 21/32134 (2013.01); H01L 29/0847 (2013.01); H01L 29/20 (2013.01); H01L 29/201 (2013.01); H01L 29/452 (2013.01); H01L 29/665 (2013.01); H01L 29/66522 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/7835 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01);
Abstract

A field effect transistor is provided which includes a plurality of fins, at least a portion of a given fin including a respective source region, and a raised source disposed at least partially on the fins and including III-V material. The field effect transistor further includes a diffusion barrier disposed at least partially on the raised source and including transition metal bonded with silicon or germanium, and a gate stack capacitively coupled at least to the respective source regions of the fins.

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