The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 06, 2018

Filed:

Jun. 27, 2017
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Osvaldo Jorge Lopez, Annandale, NJ (US);

Jonathan Almeria Noquil, Bethlehem, PA (US);

Tom Grebs, Bethlehem, PA (US);

Simon John Molloy, Allentown, PA (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/52 (2006.01); H01L 21/48 (2006.01); H01L 23/13 (2006.01); H01L 23/14 (2006.01); H01L 23/00 (2006.01); H01L 23/373 (2006.01);
U.S. Cl.
CPC ...
H01L 23/147 (2013.01); H01L 21/481 (2013.01); H01L 21/4846 (2013.01); H01L 23/13 (2013.01); H01L 23/3738 (2013.01); H01L 24/83 (2013.01); H01L 24/97 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/32225 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1425 (2013.01); H01L 2924/157 (2013.01); H01L 2924/15153 (2013.01);
Abstract

A packaged transistor device () comprises a semiconductor chip () including a transistor with terminals distributed on the first and the opposite second chip side; and a slab () of low-grade silicon (l-g-Si) configured as a ridge () framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth () at least equal to the chip thickness, the ridge covered by device terminals () connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals () of the opposite second chip side are co-planar with the device terminals on the slab ridge.


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