The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 30, 2018

Filed:

Dec. 18, 2015
Applicants:

Shin-etsu Handotai Co., Ltd., Tokyo, JP;

Sanken Electric Co., Ltd., Niiza-shi, Saitama, JP;

Inventors:

Kazunori Hagimoto, Takasaki, JP;

Masaru Shinomiya, Annaka, JP;

Keitaro Tsuchiya, Takasaki, JP;

Hirokazu Goto, Minato-ku, JP;

Ken Sato, Miyoshi-machi, JP;

Hiroshi Shikauchi, Niiza, JP;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 27/108 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/778 (2006.01); H01L 29/20 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02513 (2013.01); H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/02458 (2013.01); H01L 21/02507 (2013.01); H01L 29/7786 (2013.01); H01L 29/78 (2013.01); H01L 29/2003 (2013.01);
Abstract

An epitaxial substrate for electronic devices, including: a Si-based substrate; an AlN initial layer provided on the Si-based substrate; and a buffer layer provided on the AlN initial layer, wherein the roughness Sa of the surface of the AlN initial layer on the side where the buffer layer is located is 4 nm or more. As a result, an epitaxial substrate for electronic devices, in which V pits in a buffer layer structure can be suppressed and longitudinal leakage current characteristics can be improved when an electronic device is fabricated therewith, is provided.


Find Patent Forward Citations

Loading…