The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2018

Filed:

Aug. 31, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Shahab Siddiqui, Cifton Park, NY (US);

Abu Naser Zainuddin, Clifton Park, NY (US);

Beth Baumert, Ballston Lake, NY (US);

Suresh Uppal, Clifton Park, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/306 (2006.01); C23C 16/455 (2006.01); C01B 33/149 (2006.01); C01B 21/06 (2006.01); C01F 7/02 (2006.01); C01F 17/00 (2006.01);
U.S. Cl.
CPC ...
C23C 16/45536 (2013.01); C01B 21/0602 (2013.01); C01B 33/149 (2013.01); H01L 21/0228 (2013.01); H01L 21/30604 (2013.01); C01F 7/02 (2013.01); C01F 17/0043 (2013.01);
Abstract

Methods of forming conformal low temperature gate oxides on a HV I/O and a core logic and the resulting devices are provided. Embodiments include providing a HV I/O and core logic laterally separated on a Si substrate, each having a fin; forming a gate oxide layer over each fin and the Si substrate; forming a silicon oxy-nitride layer over the gate oxide layer; forming a sacrificial oxide layer over the silicon oxy-nitride layer; removing the sacrificial oxide and silicon oxy-nitride layers and thinning the gate oxide layer; forming a second gate oxide layer over the thinned gate oxide layer; forming a silicon oxy-nitride layer over the second gate oxide layer; removing the silicon oxy-nitride and second gate oxide layers over the core logic fin portion; forming an IL over the core logic fin portion; and forming a HfOlayer over the second silicon oxy-nitride layer and ILs.

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