The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2018
Filed:
Feb. 23, 2017
Pdf Solutions, Inc., San Jose, CA (US);
Yih-Yuh Doong, Zhubei, TW;
Chao-Hsiung Lin, Zhubei, TW;
Sheng-Che Lin, BaoShan Township, TW;
Shihpin Kuo, Tainan, TW;
Tzupin Shen, Hsinchu, TW;
Chia-Chi Lin, Hsinchu, TW;
Kimon Michaels, Monte Sereno, CA (US);
PDF Solutions, Inc., Santa Clara, CA (US);
Abstract
A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.