The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Mar. 24, 2015
Applicant:

Efficient Power Conversion Corporation, El Segundo, CA (US);

Inventors:

Robert Strittmatter, Tujunga, CA (US);

Seshadri Kolluri, San Jose, CA (US);

Robert Beach, La Crescenta, CA (US);

Jianjun Cao, Torrance, CA (US);

Alana Nakata, Redondo Beach, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); B23K 1/00 (2006.01); B23K 3/047 (2006.01); B23K 3/06 (2006.01); H01L 23/482 (2006.01); B23K 101/42 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); B23K 1/0004 (2013.01); B23K 1/0016 (2013.01); B23K 3/047 (2013.01); B23K 3/0623 (2013.01); H01L 23/4824 (2013.01); H01L 24/83 (2013.01); B23K 2201/42 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 2224/1312 (2013.01); H01L 2224/13013 (2013.01); H01L 2224/13111 (2013.01); H01L 2224/13116 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/2912 (2013.01); H01L 2224/29012 (2013.01); H01L 2224/29013 (2013.01); H01L 2224/29111 (2013.01); H01L 2224/29116 (2013.01); H01L 2224/32227 (2013.01); H01L 2224/8112 (2013.01); H01L 2224/81234 (2013.01); H01L 2224/81447 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/8312 (2013.01); H01L 2224/83447 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/1461 (2013.01);
Abstract

A method and system for electrically connect a semiconductor device with a flip-chip form factor to a printed circuit board. An exemplary embodiment of the method comprises: aligning solder contacts on the device with a first copper contact and a second copper contact of the external circuitry, and, applying a supply current only directly to a buried layer of the first copper and not directly to the layer which is nearest the device, such that no current is sourced to the device through the layer nearest the device.


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