The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2018
Filed:
Mar. 28, 2017
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/544 (2006.01); H01L 21/78 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/573 (2013.01); H01L 21/4853 (2013.01); H01L 21/56 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/544 (2013.01); H01L 2223/54453 (2013.01);
Abstract
A microelectronic package may be fabricated with debug access ports formed either at a side or at a bottom of the microelectronic package. In one embodiment, the debug access ports may be formed within an encapsulation material proximate the microelectronic package side. In another embodiment, the debug access ports may be formed in a microelectronic interposer of the microelectronic package proximate the microelectronic package side. In a further embodiment, the debug access ports may be formed at the microelectronic package bottom and may include a solder contact.