The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 02, 2018

Filed:

Mar. 07, 2017
Applicant:

Ibiden Co., Ltd., Ogaki, JP;

Inventors:

Hajime Sakamoto, Ogaki, JP;

Keisuke Shimizu, Ogaki, JP;

Assignee:

IBIDEN CO., LTD., Ogaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/482 (2006.01); H01L 23/485 (2006.01); H01L 23/538 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 23/522 (2013.01); H01L 21/4857 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/48 (2013.01); H01L 23/485 (2013.01); H01L 23/4827 (2013.01); H01L 23/49811 (2013.01); H01L 23/49822 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/76 (2013.01); H01L 24/82 (2013.01); H01L 23/562 (2013.01); H01L 2221/68359 (2013.01); H01L 2221/68372 (2013.01); H01L 2224/19 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92244 (2013.01); H01L 2924/18162 (2013.01);
Abstract

A wiring substrate includes insulating layers including a first insulating layer and an outermost insulating layer such that the first insulating layer is positioned at one end of the insulating layers in a lamination direction and that the outermost insulating layer is positioned at the opposite end of the insulating layers in the lamination direction and includes a reinforcing material; conductive layers laminated on the insulating layers such that the conductive layers include an outermost conductive layer formed on the outermost insulating layer and including pads, and a semiconductor element accommodated in an accommodating portion of the first insulating layer. The insulating layers are formed such that the insulating layers do not contain a reinforcing material other than the outermost insulating layer.


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