The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2018

Filed:

Oct. 14, 2016
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Kuan-Hsun Chen, Tainan, TW;

Ming-Shan Lo, Hsinchu, TW;

Ting-Ting Su, Taipei, TW;

Assignee:

eMemory Technology Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); G11C 16/14 (2006.01); H01L 29/423 (2006.01); H01L 29/45 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); H01L 29/42328 (2013.01); H01L 29/452 (2013.01); H01L 29/7834 (2013.01); H01L 29/7881 (2013.01); H01L 29/7885 (2013.01);
Abstract

A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.


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