The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2018

Filed:

May. 04, 2015
Applicant:

Advanced Semiconductor Engineering, Inc., Kaosiung, TW;

Inventors:

Chih-Cheng Lee, Kaohsiung, TW;

Yuan-Chang Su, Kaohsiung, TW;

Yu-Lin Shih, Kaohsiung, TW;

You-Lung Yen, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/48 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 21/481 (2013.01); H01L 23/3121 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 21/568 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/92144 (2013.01);
Abstract

The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a component within the encapsulation layer, a first dielectric layer, a second dielectric layer, a first patterned conductive layer, and a second patterned conductive layer. The component includes pads on a front surface of the component. The first dielectric layer is disposed on a surface of the encapsulation layer. The second dielectric layer is disposed on a surface of the first dielectric layer. The first and second dielectric layers define via holes extending from the second dielectric layer to respective ones of the pads. The first patterned conductive layer is disposed within the first dielectric layer and surrounds the via holes. The second patterned conductive layer is disposed within the second dielectric layer and surrounds the via holes.


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