The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Feb. 19, 2016
Applicant:

Floadia Corporation, Kodaira-shi, Tokyo, JP;

Inventors:

Hideo Kasai, Tokyo, JP;

Yasuhiro Taniguchi, Tokyo, JP;

Yasuhiko Kawashima, Tokyo, JP;

Ryotaro Sakurai, Tokyo, JP;

Yutaka Shinagawa, Tokyo, JP;

Tatsuro Toya, Tokyo, JP;

Takanori Yamaguchi, Tokyo, JP;

Fukuo Owada, Tokyo, JP;

Shinji Yoshida, Tokyo, JP;

Teruo Hatada, Tokyo, JP;

Satoshi Noda, Tokyo, JP;

Takafumi Kato, Tokyo, JP;

Tetsuya Muraya, Tokyo, JP;

Kosuke Okuyama, Tokyo, JP;

Assignee:

FLOADIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 27/112 (2006.01); H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01); H01L 23/5252 (2013.01);
Abstract

In a semiconductor memory device, voltage application from a memory gate electrode of the memory capacitor to a word line can be blocked by a rectifier element depending on values of voltages applied to the memory gate electrode and the word line without using a conventional control circuit. The configuration eliminates the need to provide a switch transistor and a switch control circuit for turning on and off the switch transistor as in conventional cases, and accordingly achieves downsizing. In the semiconductor memory device, for example, each bit line contact is shared by four anti-fuse memories adjacent to each other and each word line contact is shared by four anti-fuse memories adjacent to each other, thereby achieving downsizing of the entire device as compared to a case in which the bit line contact and the word line contact are individually provided to each anti-fuse memory.


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