The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2018

Filed:

Jun. 15, 2017
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-shi, Nagano-ken, JP;

Inventors:

Kosuke Tsukamoto, Nagano, JP;

Noriyoshi Shimizu, Nagano, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49822 (2013.01); H01L 21/481 (2013.01); H01L 21/486 (2013.01); H01L 21/4857 (2013.01); H01L 23/49811 (2013.01); H01L 23/49827 (2013.01); H01L 23/49838 (2013.01);
Abstract

A wiring substrate includes a first wiring layer, an insulative resin first insulation layer covering the first wiring layer, and a second wiring layer located on an upper surface of the first insulation layer. A via wiring layer, which extends through the first insulation layer to connect the first and second wiring layers, includes an upper end surface connected to the second wiring layer and flush with the upper surface of the first insulation layer. The second wiring layer has a higher wiring density than the first wiring layer. The first insulation layer includes a first resin layer and a second resin layer located on an upper surface of the first resin layer and having a lower filler content rate than the first resin layer. The upper surface of the first resin layer is a curved surface upwardly curved toward the upper end surface of the via wiring layer.


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