The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2018
Filed:
Jan. 25, 2017
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Yu-Ting Hsiao, Tainan, TW;
Cheng-Ta Wu, Chiayi County, TW;
Lun-Kuang Tan, Hsinchu, TW;
Liang-Yu Yen, Tainan, TW;
Ting-Chun Wang, Tainan, TW;
Tsung-Han Wu, Tainan, TW;
Wei-Ming You, Taipei, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 23/535 (2006.01); H01L 29/66 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/3215 (2013.01); H01L 23/535 (2013.01); H01L 29/0649 (2013.01); H01L 29/41791 (2013.01); H01L 29/42376 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01);
Abstract
A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.