The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2018
Filed:
Oct. 11, 2016
Applicant:
Macronix International Co., Ltd., Hsinchu, TW;
Inventors:
Chi-Pin Lu, Hsinchu, TW;
Pei-Ci Jhang, New Taipei, TW;
Fu-Hsing Chou, New Taipei, TW;
Chih-Hsiung Lee, Hsinchu, TW;
Assignee:
MACRONIX INTERNATIONAL CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 27/11521 (2017.01); H01L 27/11526 (2017.01); H01L 29/04 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/027 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H01L 29/36 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/0273 (2013.01); H01L 21/02164 (2013.01); H01L 21/02282 (2013.01); H01L 21/30604 (2013.01); H01L 21/31111 (2013.01); H01L 21/76224 (2013.01); H01L 21/76802 (2013.01); H01L 27/11526 (2013.01); H01L 29/045 (2013.01); H01L 29/0649 (2013.01); H01L 29/36 (2013.01);
Abstract
A method of manufacturing an integrated circuit including forming trenches into the surface of a crystalline wafer and the trenches extending along a <100> lattice direction is disclosed. Such wafer can experience less deformation due to less stress induced when the trenches are filled using a spin-on dielectric material. Thus, the overlay issue caused by wafer shape change is resolved.