The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2018
Filed:
Jan. 29, 2016
Applicant:
Kilopass Technology, Inc., San Jose, CA (US);
Inventors:
Harry Luan, Saratoga, CA (US);
Bruce L. Bateman, Fremont, CA (US);
Valery Axelrad, Woodside, CA (US);
Charlie Cheng, Los Altos, CA (US);
Christophe J. Chevallier, Palo Alto, CA (US);
Assignee:
Kilopass Technology, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 21/8229 (2006.01); H01L 21/8249 (2006.01); H01L 27/102 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/732 (2006.01); H01L 29/74 (2006.01); G11C 11/39 (2006.01); H01L 29/745 (2006.01); G11C 11/41 (2006.01); H01L 27/06 (2006.01); H01L 27/082 (2006.01); G11C 11/411 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); G11C 11/39 (2013.01); G11C 11/41 (2013.01); H01L 21/8229 (2013.01); H01L 21/8249 (2013.01); H01L 27/0623 (2013.01); H01L 27/1025 (2013.01); H01L 27/1027 (2013.01); H01L 27/11 (2013.01); H01L 27/1116 (2013.01); H01L 29/0649 (2013.01); H01L 29/083 (2013.01); H01L 29/0804 (2013.01); H01L 29/0847 (2013.01); H01L 29/1004 (2013.01); H01L 29/1012 (2013.01); H01L 29/1095 (2013.01); H01L 29/66272 (2013.01); H01L 29/66386 (2013.01); H01L 29/732 (2013.01); H01L 29/742 (2013.01); H01L 29/7455 (2013.01); G11C 11/411 (2013.01); H01L 27/0821 (2013.01); H01L 27/0826 (2013.01);
Abstract
A memory cell based upon thyristors for an SRAM integrated circuit can be implemented in different combinations of MOS and bipolar select transistors, or without select transistors, with thyristors in a semiconductor substrate with shallow trench isolation. Standard CMOS process technology can be used to manufacture the SRAM cells. Special circuitry provides lowered power consumption during standby.