The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Dec. 30, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brennan J. Brown, Burlington, VT (US);

Natalie B. Feilchenfeld, Jericho, VT (US);

Max G. Levy, Essex Junction, VT (US);

Santosh Sharma, Essex Junction, VT (US);

Yun Shi, South Burlington, VT (US);

Michael J. Zierak, Colchester, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42368 (2013.01); H01L 29/0649 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01);
Abstract

Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.


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