The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2018

Filed:

Sep. 30, 2015
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Jung-Ping Yang, Jui-bei, TW;

Hong-Chen Cheng, Hsinchu, TW;

Chih-Chieh Chiu, Toufen Township, TW;

Chia-En Huang, Xinfeng Township, TW;

Cheng Hung Lee, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/12 (2006.01); G11C 7/18 (2006.01); G11C 11/419 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); G11C 7/18 (2013.01); G11C 11/419 (2013.01); G11C 2207/005 (2013.01);
Abstract

A memory includes a plurality of memory blocks, a plurality of sensing circuits, a plurality of global bit lines, a common pre-charging circuit and a selection circuit. Each global bit line of the plurality of global bit lines is coupled to at least one of the memory blocks by a corresponding sensing circuit of the plurality of sensing circuits. The common pre-charging circuit is configured to individually pre-charge each global bit line of the plurality of global bit lines to a pre-charge voltage. The selection circuit is configured to selectively couple the common pre-charging circuit to a selected global bit line of the plurality of global bit lines.


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