The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 31, 2018
Filed:
Oct. 06, 2015
Floadia Corporation, Kodaira-shi, Tokyo, JP;
Yutaka Shinagawa, Kodaira, JP;
Yasuhiro Taniguchi, Kodaira, JP;
Hideo Kasai, Kodaira, JP;
Ryotaro Sakurai, Kodaira, JP;
Yasuhiko Kawashima, Kodaira, JP;
Tatsuro Toya, Kodaira, JP;
Kosuke Okuyama, Koadira, JP;
FLOADIA CORPORATION, Tokyo, JP;
Abstract
A voltage applied to a bit line or to a source line is reduced to a value allowing a first or second select gate structure to block electrical connection between the bit line and a channel layer or between the source line and the channel layer, irrespective of a voltage needed to inject charge into a charge storage layer by a quantum tunneling effect. In accordance with the reduction in voltage(s) applied to the bit line and the source line, thickness of each of a first and second select gate insulating films of the first and second select gate structure is reduced. High-speed operation is achieved correspondingly. With the reduction in voltage(s) applied to the bit and source lines, thickness of a gate insulating film of a field effect transistor in a peripheral circuit controlling a memory cell is reduced. The area of the peripheral circuit is reduced correspondingly.