The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Feb. 21, 2017
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Stmicroelectronics, Inc., Coppell, TX (US);

Inventors:

Stephane Allegret-Maret, Grenoble, FR;

Kangguo Cheng, Schenectady, NY (US);

Bruce Doris, Slingerlands, NY (US);

Prasanna Khare, Schenectady, NY (US);

Qing Liu, Guilderland, NY (US);

Nicolas Loubet, Guilderland, NY (US);

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 27/11 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66772 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 27/1104 (2013.01);
Abstract

An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.


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