The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Sep. 19, 2016
Applicant:

Sandisk Technologies Llc, Plano, TX (US);

Inventors:

Yoko Furihata, Yokkaichi, JP;

Jixin Yu, Milpitas, CA (US);

Hiroyuki Ogawa, Yokkaichi, JP;

James Kai, Santa Clara, CA (US);

Jin Liu, Milpitas, CA (US);

Johann Alsmeier, San Jose, CA (US);

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/792 (2006.01); H01L 27/11582 (2017.01); H01L 23/528 (2006.01); H01L 27/11575 (2017.01); H01L 27/11573 (2017.01); H01L 27/11565 (2017.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/11556 (2017.01); H01L 27/1157 (2017.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/76802 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76877 (2013.01); H01L 21/76895 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0288 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11573 (2013.01); H01L 27/11575 (2013.01);
Abstract

A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating layers located over the word line driver devices, a plurality of memory stack structures extending through the alternating stack, each memory stack structure including a memory film and a vertical semiconductor channel, and through-memory-level via structures which electrically couple the word lines in a first memory block to the word line driver devices. The through-memory-level via structures extend through a through-memory-level via region located between a staircase region of the first memory block and a staircase region of another memory block.


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