The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 31, 2018

Filed:

Nov. 29, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Wan Hsuan Hsu, Taoyuan, TW;

I-Hsiu Wang, Yongkang, TW;

Yean-Zhaw Chen, Tainan, TW;

Cheng-Wei Chang, Hsin-Chu, TW;

Yu Shih Wang, Tainan, TW;

Hsin-Yan Lu, New Taipei, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/311 (2006.01); H01L 21/027 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 27/02 (2006.01); H01L 29/08 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/0217 (2013.01); H01L 21/0274 (2013.01); H01L 21/02178 (2013.01); H01L 21/31144 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/823425 (2013.01); H01L 21/823468 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/0847 (2013.01); H01L 29/41758 (2013.01);
Abstract

A method includes forming a first transistor and a second transistor over a substrate, wherein the first transistor and the second transistor share a drain/source region formed between a first gate of the first transistor and a second gate of the second transistor, forming a first opening in an interlayer dielectric layer and between the first gate and the second gate, depositing an etch stop layer in the first opening and on a top surface of the interlayer dielectric layer, depositing a dielectric layer over the etch stop layer, applying a first etching process to the dielectric layer until the etch stop layer is exposed, performing a second etching process on the etch stop layer until an exposed portion of the etch stop layer and portions of the dielectric layer have been removed.


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