The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 26, 2018

Filed:

Sep. 16, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ru-Shang Hsiao, Jhubei, TW;

Ling-Sung Wang, Tainan, TW;

Chih-Mu Huang, Tainan, TW;

Cing-Yao Chan, Keelung, TW;

Chun-Ying Wang, Tainan, TW;

Jen-Pan Wang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 27/092 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/8238 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0928 (2013.01); H01L 21/02381 (2013.01); H01L 21/02529 (2013.01); H01L 21/02532 (2013.01); H01L 21/02694 (2013.01); H01L 21/30604 (2013.01); H01L 21/823807 (2013.01); H01L 29/0653 (2013.01); H01L 29/1054 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/66545 (2013.01); H01L 29/66575 (2013.01); H01L 29/66651 (2013.01); H01L 29/7842 (2013.01);
Abstract

The present disclosure relates to a transistor device having a channel region comprising a sandwich film stack with a plurality of different layers that improve device performance, and an associated apparatus. In some embodiments, the transistor device has a source region and a drain region disposed within a semiconductor substrate. A sandwich film stack is laterally positioned between the source region and the drain region. The sandwich film stack has a lower layer, a middle layer of a carbon doped semiconductor material disposed over the lower layer, and an upper layer disposed over the middle layer. A gate structure is disposed over the sandwich film stack. The gate structure is configured to control a flow of charge carriers in a channel region located between the source region and the drain region.


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