The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2018
Filed:
Jul. 08, 2016
Avago Technologies General Ip (Singapore) Pte. Ltd., Singapore, SG;
Sam Ziqun Zhao, Irvine, CA (US);
Sam Komarapalayam Karikalan, Irvine, CA (US);
Edward Law, Ladera Ranch, CA (US);
Rezaur Rahman Khan, Irvine, CA (US);
Pieter Vorenkamp, Laguna Niguel, CA (US);
Avago Technologies General IP (Singapore) Pte. Ltd., Singapore, SG;
Abstract
Semiconductor devices and manufacturing methods are provided for using a Recon interposer that provides a high density interface between the active semiconductor die and the semiconductor substrate and also provides the pitch fan-out. For example, a circuit assembly includes a silicon pad layer including a plurality of metal pads, each metal pad configured to receive a corresponding bump of a plurality of bumps. The circuit assembly further includes an oxide layer disposed on the silicon pad layer and an interposer dielectric layer disposed on the oxide layer. The interposer dielectric layer includes a plurality of routing traces that connect a top surface of the redistribution layer to a bottom surface of the interposer dielectric layer. The circuit assembly further includes an integrated circuit (IC) die attached to the plurality of routing traces at the top surface of the interposer dielectric layer using a plurality of IC bumps and an encapsulating material encapsulating at least a portion of the silicon pad layer, the oxide layer, the interposer dielectric layer, and the IC die to provide structural support for the circuit assembly.