Zhubei, Taiwan

Zhi-Sheng Hsu


Average Co-Inventor Count = 5.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2021

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1 patent (USPTO):

Title: Zhi-Sheng Hsu: Innovator in Semiconductor Technology

Introduction

Zhi-Sheng Hsu is a prominent inventor based in Zhubei, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly through his innovative patent. His work is instrumental in advancing the efficiency and effectiveness of semiconductor device structures.

Latest Patents

Zhi-Sheng Hsu holds a patent for a "Polishing process for forming semiconductor device structure." This method involves providing a wafer over a polishing platen, where the wafer consists of a metal layer and a dielectric layer. The metal layer covers the dielectric layer and fills an opening of the dielectric layer. The process includes polishing the wafer using a first operation to thin down the metal layer, which has a specific polishing selectivity of the metal layer to the dielectric layer. A second operation further thins down the metal layer until the dielectric layer is exposed, with a different polishing selectivity from the first operation. Both operations are performed in-situ on the polishing platen, showcasing a sophisticated approach to semiconductor manufacturing.

Career Highlights

Zhi-Sheng Hsu is associated with Taiwan Semiconductor Manufacturing Company Limited, a leading entity in the semiconductor industry. His role in this esteemed company highlights his expertise and commitment to innovation in semiconductor technology.

Collaborations

Zhi-Sheng Hsu has collaborated with notable colleagues, including Shih-Ho Lin and Jen-Chieh Lai. These collaborations reflect a strong network of professionals dedicated to advancing semiconductor technologies.

Conclusion

Zhi-Sheng Hsu's contributions to semiconductor technology through his innovative patent demonstrate his significant role in the industry. His work continues to influence the development of efficient semiconductor device structures.

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