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Santa Clara, CA, United States of America

Zarir B Sarkari

This inventor holds 5 USPTO granted patents. Top assignee: Lsi Logic Corporation. Active years: 1997-2002.

USPTO Granted Patents = 5

% Patents Active = 100.0

Average Co-Inventor Count = 4.2

ph-index = 4

Forward Citations = 78(Granted Patents)

Location History:

Santa Clara, CA (US) (1997)
San Jose, CA (US) (1997 - 2002)

Company Filing History:

Lsi Logic Corporation

Years Active: 1997-2002

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5 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6345378 - Synthesis shell generation and use in ASIC design (2002-02-05),

2. 5844818 - Method for creating and using design shells for integrated circuit (1998-12-01),

3. 5670890 - Switchable pull-ups and pull-downs for IDDQ testing of integrated (1997-09-23),

4. 5644498 - Timing shell generation through netlist reduction (1997-07-01),

5. 5644251 - Switchable pull-ups and pull-downs for IDDQ testing of integrated (1997-07-01),

Profile summary based on public USPTO records.

Please report any incorrect information to [email protected]

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