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Yves Thomas Laplanche

USPTO Granted Patents = 11 (Patent Applications = 3)

Average Co-Inventor Count = 2.3

ph-index = 3

Forward Citations = 24(Granted Patents)

Location History:

Crolles, FR (2007 - 2015)
Austin, TX (US) (2019 - 2022)
Valbonne, FR (2024)

Company Filing History:

Stmicroelectronics S.a.

patents

1 out of 3,559

Commissariat a L'energie Atomique

patents

where one patent can have more than one assignee

Years Active: 2007-2025

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11 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12352826 - Current measurement architecture (2025-07-08),

2. 12068745 - Multi-bit scan chain with error-bit generator (2024-08-20),

3. 11900041 - Via coloring methods and systems (2024-02-13),

4. 11315927 - Cell bridging technique (2022-04-26),

5. 10355674 - Clock gating circuit (2019-07-16),

6. 9105315 - Controlling the voltage level on the word line to maintain performance and reduce access disturbs (2015-08-11),

7. 8924766 - Analysing timing paths for circuits formed of standard cells (2014-12-30),

8. 8779787 - Apparatus and method for determining variation in a predetermined physical property of a circuit (2014-07-15),

9. 8252638 - Method for forming under a thin layer of a first material portions of another material and/or empty areas (2012-08-28),

10. 8219950 - Propagation delay time balancing in chained inverting devices (2012-07-10),

11. 7202153 - Method for forming, under a thin layer of a first material, portions of another material and/or empty areas (2007-04-10),

Title: Yves Thomas Laplanche: Innovator in Current Measurement and Multi-Bit Scan Chain Technologies

Introduction

Yves Thomas Laplanche is a notable inventor based in Crolles, France. He holds a total of 11 patents that showcase his contributions to the fields of electronics and device architecture. His innovative work has significantly impacted the design and functionality of various electronic devices.

Latest Patents

Among his latest patents, one is titled "Current Measurement Architecture." This invention relates to a device with fabrication test circuitry featuring transistors arranged in a parallel branch configuration between a supply voltage and a single pad. In specific applications, each transistor in an off-current branch can be separately deactivated to test leakage current applied to the pad. Additionally, each transistor in an on-current branch may also be deactivated to further assess the leakage current applied to the pad.

Another significant patent is "Multi-Bit Scan Chain with Error-Bit Generator." This invention describes a device that includes a scan chain receiving a multi-bit input and providing a multi-bit output. The device also features a multi-bit multiplexer output based on the multi-bit input and output. An error-bit generator is incorporated, which receives the multi-bit multiplexer output, a portion of the multi-bit input, and a portion of the multi-bit output to provide an error-bit output.

Career Highlights

Yves has worked with prominent companies in the technology sector, including Arm Limited and STMicroelectronics S.A. His experience in these organizations has allowed him to develop and refine his innovative ideas, contributing to advancements in electronic device design.

Collaborations

Throughout his career, Yves has collaborated with talented individuals such as Philippe Coronel and Laurent Pain. These partnerships have fostered a creative environment that has led to the development of groundbreaking technologies.

Conclusion

Yves Thomas Laplanche is a distinguished inventor whose work in current measurement and multi-bit scan chain technologies has made a lasting impact on the electronics industry. His innovative patents and collaborations reflect his commitment to advancing technology and improving device functionality.

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