Arm Limited

Stmicroelectronics S.a.

Commissariat a L'energie Atomique

Yves Thomas Laplanche

Philippe Coronel

Anil Kumar Baratam

Laurent Pain

Abhilash Velluridathil Thazhathidathil

Betina Hold

Jean-Luc Pelloie

Ramesh Manohar

Kenza Charafeddine

Sreejith Mohan

Jean Luc Pelloie

Ashwani Kumar Srivastava

Buchupalli Venkata Chaitanya Reddy

Nruthya Nagesh Prabhu

Ala Srinivasa Rao

Various implementations described herein are related to a device with fabrication test circuitry having transistors arranged in a parallel branch configuration between a supply voltage and a single pad. In some applications, each transistor in an off-current branch may be separately deactivated so as to test leakage current applied to the pad by way of the off-current branch, and also, each transistor in an on-current branch may be deactivated so as to further test the leakage current applied to the pad by way of the off-current branch.

Current measurement architecture

Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.

Multi-bit scan chain with error-bit generator

In a particular implementation, a method includes: identifying prospective zones for placement of one or more vertical interconnect access pads (via) in a cell, where each of the prospective zones comprises one or more poly pitches; and assigning a first color for a particular poly pitch of a first identified zone of the identified prospective zones or assigning a first color sequence for one or more sections of the first identified zone.

Via coloring methods and systems

Various implementations described herein are directed to device having a regular well cell and a flipped well cell. The regular well cell has a first N-well and a first P-well, and the flipped well cell has a second N-well and a second P-well in complementary relationship with the first N-well and the first P-well of the regular well cell. The device includes a bridge cell disposed between the regular well cell and the flipped well cell.

Cell bridging technique

Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

Clock gating circuit

A semiconductor memory storage device for storing data including: a plurality of storage cells, each storage cell including an access control device configured to provide the storage cell with access to or isolation from a data access port in response to an access control signal. Access control circuitry includes: access switching circuitry configured to connect a selected access control line to a voltage source; and feedback circuitry configured to feedback a change in voltage on the access control line to the access switching circuitry. The access control circuitry is configured to respond to a data access request signal to access a selected storage cell connected to a corresponding selected access control line in response to the feedback circuitry providing a feedback signal indicating that the access control line voltage has attained a predetermined value.

Controlling the voltage level on the word line to maintain performance and reduce access disturbs

A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterization data for the cell. The correcting steps includes providing further characterization data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Analysing timing paths for circuits formed of standard cells

Apparatus and method for determining variation in a predetermined physical property of a circuit. The apparatus includes monitored circuitry for generating output pulses, and configured such that each output pulse has a pulse width which is indicative of the current value of the predetermined physical property. Circuitry is then configured to receive both the output pulses generated by the monitored circuitry and an oscillating timing reference signal. With reference to the oscillating timing reference signal, the counter circuitry produces for each output pulse an associated count value indicative of the pulse width of that output pulse. Circuitry then compares the associated count values for at least two output pulses, in order to produce a comparison result used to determine the variation in the predetermined physical property. This provides a flexible mechanism for monitoring variations in a physical property on the fly during use of a data processing circuit.

Apparatus and method for determining variation in a predetermined physical property of a circuit

A method for forming an empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.

Method for forming under a thin layer of a first material portions of another material and/or empty areas

A circuit comprising a plurality of semiconductor inverting devices arranged in series is disclosed. Each of the semiconductor inverting devices comprise at least one NMOS transistor and at least one PMOS transistor and alternate ones of the inverting devices in the series comprise transistors having a first ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; and alternate ones of said inverting devices in the series comprise transistors having a second ratio of a width of the at least one PMOS transistor and the at least one NMOS transistor; wherein the first ratio and the second ratio are not equal and in some case, the first and second ratios are such that a sum of a delay in a rise time of a signal propagated by a first inverting device and a fall time of a signal propagated by a second inverting device is substantially equal to a delay in a fall time of a signal propagated by the first inverting device.

Propagation delay time balancing in chained inverting devices

A method for forming a empty area under a layer of a given material, including forming on a substrate a stacking of a photosensitive layer and of a layer of the given material; insolating a portion of the photosensitive layer or its complement according to whether the photosensitive layer is positive or negative with an electron beam crossing the layer of the given material; and removing the portion of the photosensitive layer.

Growing community of inventors

Crolles, France

Yves Thomas Laplanche