Hsinchu, Taiwan

Yung-Chang Lien

This inventor holds 2 USPTO granted patents and 1 published patent application and 1 EPO patent. Top assignee: Mediatek Corporation. Active years: 2022-2024.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yung-Chang Lien. Retrieved from https://idiyas.com/inventor/yung-chang-lien

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 2 

% Patents Active = 100.0

 

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 3(Granted Patents)


Company Filing History:


Years Active: 2022-2024

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2 patents (USPTO):Explore Patents

Title: Yung-Chang Lien: Innovator in Semiconductor Packaging

Introduction

Yung-Chang Lien is a notable inventor based in Hsinchu, Taiwan. He has made significant contributions to the field of semiconductor packaging, holding a total of 2 patents. His work focuses on enhancing the efficiency and functionality of semiconductor devices.

Latest Patents

Yung-Chang Lien's latest patents include a semiconductor package structure. This innovative structure comprises a substrate, a frame, a redistribution layer, and a first semiconductor die. The substrate features a wiring structure and is encased in a molding material. The frame is positioned within the molding material, surrounding the substrate. The redistribution layer is placed over the substrate and is electrically connected to the wiring structure. Finally, the first semiconductor die is situated atop the redistribution layer.

Career Highlights

Yung-Chang Lien is currently employed at MediaTek Corporation, a leading company in the semiconductor industry. His role involves developing advanced packaging solutions that contribute to the performance of electronic devices.

Collaborations

Yung-Chang Lien collaborates with Tzu-Hung Lin, a fellow innovator in the field. Together, they work on projects that push the boundaries of semiconductor technology.

Conclusion

Yung-Chang Lien's contributions to semiconductor packaging demonstrate his commitment to innovation and excellence in technology. His patents reflect a deep understanding of the complexities involved in semiconductor design and manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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