Ohra-gun, Japan

Yukio Kanno


Average Co-Inventor Count = 1.7

ph-index = 4

Forward Citations = 56(Granted Patents)


Location History:

  • Ohra-gun, JP (1998 - 1999)
  • Ootone-machi, JP (1999)
  • Gyoda, JP (2000)

Company Filing History:


Years Active: 1998-2000

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4 patents (USPTO):Explore Patents

Title: Innovations by Yukio Kanno in Semiconductor Testing Technology

Introduction

Yukio Kanno is a notable inventor based in Ohra-gun, Japan. He has made significant contributions to the field of semiconductor testing technology. With a total of 4 patents to his name, Kanno's work has advanced the efficiency and effectiveness of integrated circuit (IC) testing.

Latest Patents

Kanno's latest patents include innovative designs for semiconductor device testing apparatuses. One of his inventions involves an IC tester that prevents the temperature of an IC, heated to a predetermined level, from falling during testing. This design features a box-like housing made of thermally insulating material, which is mounted on a performance board. The housing accommodates an IC socket and a socket guide, ensuring that the testing environment remains thermally insulated. Another patent describes an IC tester that utilizes a planar heater plate to heat ICs before testing. This design includes a movable shutter that exposes IC receiving recesses, allowing for efficient testing operations.

Career Highlights

Yukio Kanno is currently employed at Adv Antest Corporation, where he continues to innovate in the semiconductor testing field. His work has been instrumental in developing advanced testing solutions that enhance the reliability of semiconductor devices.

Collaborations

Kanno has collaborated with notable colleagues, including Toshio Goto and Hisao Hayama. Their combined expertise has contributed to the success of various projects within the company.

Conclusion

Yukio Kanno's contributions to semiconductor testing technology reflect his dedication to innovation and excellence. His patents demonstrate a commitment to improving the efficiency of IC testing processes.

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