Taoyuan, Taiwan

Yuan-Jou Lo

This inventor holds 1 USPTO granted patent. Top assignee: National Yang Ming Chiao Tung University. Active years: 2015.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yuan-Jou Lo. Retrieved from https://idiyas.com/inventor/yuan-jou-lo

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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Average Co-Inventor Count = 4.0

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Company Filing History:


Years Active: 2015

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1 patent (USPTO):Explore Patents

Title: Innovations of Yuan-Jou Lo in Semiconductor Fabrication

Introduction

Yuan-Jou Lo is a notable inventor based in Taoyuan County, Taiwan. He has made significant contributions to the field of semiconductor technology. His innovative methods have the potential to enhance the efficiency and performance of semiconductor devices.

Latest Patents

Yuan-Jou Lo holds a patent titled "Method for Fabricating Semiconductor Device." This patent describes a novel approach to fabricating semiconductor devices. The method involves several key steps, including the formation of a gate on a substrate, the creation of a gate insulating layer, and the placement of an active layer composed of a microwave absorbing material. Additionally, source/drain regions are defined on the active layer, culminating in a microwave annealing process to finalize the semiconductor device. He has 1 patent to his name.

Career Highlights

Yuan-Jou Lo is affiliated with National Yang Ming Chiao Tung University, where he contributes to research and development in semiconductor technologies. His work is recognized for its innovative approach and practical applications in the industry.

Collaborations

Yuan-Jou Lo has collaborated with notable colleagues, including Po-Tsun Liu and Li-Feng Teng. Their combined expertise enhances the research output and innovation potential within their projects.

Conclusion

Yuan-Jou Lo's contributions to semiconductor fabrication represent a significant advancement in the field. His innovative methods and collaborative efforts continue to influence the development of efficient semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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