Taipei, Taiwan

Yu-Che Lin

This inventor holds 1 USPTO granted patent. Top assignee: Richtek Technology Corporation. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Che Lin. Retrieved from https://idiyas.com/inventor/yu-che-lin-z88zel8g

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Yu-Che Lin: Innovator in Asymmetric Cellular CMOS Technology

Introduction

Yu-Che Lin is a prominent inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology, particularly through his innovative designs in CMOS arrays. His work focuses on enhancing the efficiency and density of cellular MOS arrays, which has implications for reducing chip size and manufacturing costs.

Latest Patents

Yu-Che Lin holds 1 patent for his invention titled "Area Efficient Asymmetric Cellular CMOS Array." This patent describes a cellular MOS array that employs an asymmetric structure. By reducing the areas of the sources without altering the length and width of the channel, the design allows for a denser array, ultimately leading to smaller chip sizes and lower production costs.

Career Highlights

Yu-Che Lin is currently employed at Richtek Technology Corporation, where he continues to develop cutting-edge technologies in the semiconductor industry. His work has positioned him as a key player in advancing CMOS technology, contributing to the company's reputation for innovation.

Collaborations

Throughout his career, Yu-Che Lin has collaborated with notable colleagues, including Chung-Lung Pai and Pao-Chuan Lin. These partnerships have fostered a creative environment that encourages the development of groundbreaking technologies.

Conclusion

In summary, Yu-Che Lin is an influential inventor whose work in asymmetric cellular CMOS technology has the potential to transform the semiconductor industry. His innovative approach not only enhances efficiency but also contributes to cost reduction in chip manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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