Suwon, South Korea

Youngrok Park

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Samsung Electronics Co., Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Youngrok Park. Retrieved from https://idiyas.com/inventor/youngrok-park

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Youngrok Park and His Patent in Semiconductor Circuit Design.

Introduction

Youngrok Park is an inventor based in Suwon, South Korea, and is associated with Samsung Electronics Ltd. His patent work concerns integrated circuit architecture and the design of wiring for memory systems.

Latest Patents

Park is named on one patent: “Integrated Circuit Including Backside Wiring and Method of Designing the Same.” The invention describes an integrated circuit with a bit cell array and frontside wiring that connects to the cells. A row decoder provides word line signals, which backside wiring carries from the decoder. A word line rebuffer then delivers those signals to local word lines connected to the bit cells. The design addresses how word line signals are routed through an integrated circuit.

Career Highlights

Park’s listed patent activity reflects work in semiconductor design at Samsung Electronics Ltd. His patent focuses on coordinating frontside and backside wiring to support word line signal delivery in a bit cell array. His record includes 1 patent.

Collaborations

Park’s listed coworkers include Hoyoung Tang and Taehyung Kim. Their names are associated with his professional context, though the available information does not specify particular joint projects.

Conclusion

Youngrok Park’s patent highlights an approach to integrated circuit design that uses backside wiring and rebuffering to route word line signals to memory cells.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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