Hino, Japan

Yoshinobu Amano

This inventor holds 1 USPTO granted patent. Top assignee: Seiko Epson Corporation. Active years: 2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yoshinobu Amano. Retrieved from https://idiyas.com/inventor/yoshinobu-amano

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2010

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1 patent (USPTO):Explore Patents

Title: The Innovations of Yoshinobu Amano

Introduction

Yoshinobu Amano is a notable inventor based in Hino, Japan. He has made significant contributions to the field of semiconductor technology. His work has led to advancements that enhance the functionality and efficiency of integrated circuit devices.

Latest Patents

Amano holds a patent for a semiconductor integrated circuit device, data recording device, and layout method for semiconductor integrated circuit devices. This innovative design features a first image data interface section located in an electrode region and an input/output buffer region along one side of a semiconductor chip. Additionally, a second image data interface section is positioned along another side, while first and second memory interface sections are strategically placed along the remaining sides. This layout optimizes the performance of semiconductor devices.

Career Highlights

Yoshinobu Amano is currently employed at Seiko Epson Corporation, where he continues to push the boundaries of technology. His work at this esteemed company has allowed him to collaborate with other talented professionals in the field.

Collaborations

One of his notable coworkers is Chisato Higuchi, with whom he has likely shared insights and expertise in their projects.

Conclusion

Yoshinobu Amano's contributions to semiconductor technology exemplify the innovative spirit of modern inventors. His patent reflects a commitment to advancing technology and improving device performance.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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