Seoul, South Korea

Yoo-suck Jung

This inventor holds 1 USPTO granted patent. Top assignee: Samsung Electronics Co., Ltd.. Active years: 1993.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yoo-suck Jung. Retrieved from https://idiyas.com/inventor/yoo-suck-jung

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 2.0

ph-index = 1

Forward Citations = 12(Granted Patents)


Company Filing History:


Years Active: 1993

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1 patent (USPTO):Explore Patents

Title: Yoo-suck Jung and Semiconductor Reflow Technology.

Introduction

Yoo-suck Jung is an inventor associated with Seoul, South Korea, and Samsung Electronics Co., Ltd. His patent work includes a method for improving the planarization of semiconductor devices through a controlled reflow process.

Latest Patents

Jung is identified with 1 patent, titled “Method of Reflowing a Semiconductor Device.” The invention describes forming insulating layers and electrodes on a silicon semiconductor substrate, followed by two borophosphosilicate glass (BPSG) layers with different concentrations of boron and phosphorus. Reflowing these layers helps flatten their surfaces before the resulting structure is etched. The patent explains that using two BPSG concentrations can lower the reflow baking temperature by as much as 50°C while helping prevent corrosive properties in the reflowed film.

Career Highlights

Jung’s documented patent contribution addresses semiconductor fabrication, particularly the planarization of layered device structures. The method combines specified BPSG compositions and layer thicknesses to support reflow at reduced temperatures.

Collaborations

The supplied information identifies Sung-Min Lee as Jung’s coworker. It does not specify Lee’s role in the patent or establish that he was a co-inventor.

Conclusion

Yoo-suck Jung’s patent describes a two-concentration BPSG reflow method intended to improve semiconductor surface planarization while reducing processing temperatures and limiting corrosive effects.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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