Yi-Ting Lee

Title: Yi-Ting Lee: Innovator in Circuit Design Technology

Introduction

Yi-Ting Lee is a prominent inventor based in Zhubei, Taiwan. She has made significant contributions to the field of circuit design technology, holding 2 patents that showcase her innovative approach to solving complex engineering challenges.

Latest Patents

One of her latest patents is titled "Automatic moving of probe locations for parasitic extraction." This invention identifies probe location candidates from geometric elements on a probe layer, which is essential for placing new probes in circuit designs. The technology ensures that the selected probe locations are conductively connected to the original probe location, allowing for accurate extraction of parasitic resistance values.

Another notable patent is "Connectivity-aware layout data reduction for design verification." This patent focuses on techniques for reducing layout data while maintaining connectivity awareness. It involves selecting circuit elements of interest and determining nets and cells based on their pins. This innovation is particularly useful for design verification, including electrostatic discharge (ESD) protection verification.

Career Highlights

Yi-Ting Lee is currently employed at Mentor Graphics Corporation, where she continues to develop cutting-edge technologies in circuit design. Her work has significantly impacted the efficiency and accuracy of design verification processes in the industry.

Collaborations

She collaborates with esteemed colleagues such as Sridhar Srinivasan and Patrick D. Gibson, contributing to a dynamic team focused on advancing circuit design methodologies.

Conclusion

Yi-Ting Lee's contributions to circuit design technology through her patents and collaborative efforts highlight her role as an influential inventor in the field. Her innovative solutions continue to shape the future of circuit design and verification.