Yi-Feng Jang

Title: Yi-Feng Jang: Innovator in Variable Length Decoding Technology

Introduction

Yi-Feng Jang is a prominent inventor based in Keelung, Taiwan. He has made significant contributions to the field of data compression, particularly in variable length decoding (VLD) technology. With a total of 4 patents to his name, Jang's work has been influential in various applications, including image data communication and storage.

Latest Patents

One of Jang's latest patents is the "VLC decoder with sign bit masking." This invention relates to a parallel variable length decoder and a method for decoding a signed variable length code word. The technique is widely used in data compression, especially in international standards such as JPEG and MPEG. The invention utilizes a single programmable logic array (PLA) that processes the sign bit outside the PLA, enhancing the efficiency of the decoding process.

Another notable patent is the "Variable length decoder using serial and parallel processing." This architecture allows a bit-serial variable length decoder to receive the coded bit stream directly without buffering. The design achieves high throughput with minimal buffer capacity, showcasing Jang's innovative approach to VLD technology.

Career Highlights

Yi-Feng Jang is affiliated with the Industrial Technology Research Institute, where he continues to advance research in variable length decoding. His work has garnered attention for its practical applications in improving data compression techniques.

Collaborations

Jang has collaborated with notable colleagues, including Po-Chuan Huang and Jinn-Nan Kao, contributing to the development of cutting-edge technologies in their field.

Conclusion

Yi-Feng Jang's contributions to variable length decoding technology have established him as a key figure in the realm of data compression. His innovative patents reflect a commitment to enhancing the efficiency of data communication and storage.