Yasunobu Kakumoto

Title: Yasunobu Kakumoto: Innovator in Semiconductor Technology

Introduction

Yasunobu Kakumoto is a notable inventor based in Kyoto, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 2 patents. His work focuses on enhancing the functionality and efficiency of electronic circuits.

Latest Patents

Kakumoto's latest patents include a muting circuit and a step-down voltage output circuit. The muting circuit is designed to suppress shot noise caused by DC differences when switching between ON and OFF states. It features an input terminal for control signals and a muting transistor that effectively manages the mute operation. The step-down voltage output circuit addresses the latch-up phenomenon in load circuits during power-supply activation. It includes a timer circuit and two N-channel MOS transistors that work together to ensure stable voltage output.

Career Highlights

Throughout his career, Yasunobu Kakumoto has worked with prominent companies such as Panasonic Corporation and Matsushita Electric Industrial Co., Ltd. His experience in these organizations has allowed him to develop innovative solutions in the semiconductor industry.

Collaborations

Kakumoto has collaborated with talented individuals like Keiichi Fujii and Taku Kobayashi. These partnerships have contributed to the advancement of his projects and the successful development of his patents.

Conclusion

Yasunobu Kakumoto is a distinguished inventor whose work in semiconductor technology has led to valuable innovations. His patents reflect his commitment to improving electronic circuit performance and reliability.