This inventor holds 1 USPTO granted patent. Top assignee: Kabushiki Kaisha Toshiba. Active years: 1999.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile
Company Filing History:
Years Active: 1999
Title: Yasuhiro Tonooka and Static-Timing Analysis for LSIs.
Introduction
Yasuhiro Tonooka is an inventor associated with Kanagawa, Japan, and Kabushiki Kaisha Toshiba. His work includes a patented system and method for analyzing static timing in large-scale integrated circuits (LSIs).
Latest Patents
Tonooka is credited with 1 patent, titled “System and Method for Analyzing Static Timing.” The invention aims to reduce processing time and limit false paths in static-timing analysis results. Its method builds an internal analysis structure from transistor-level net-list information, checks whether nodes may have high-impedance expected values, and uses those values to narrow possible signal-flow directions. It then divides a sequential circuit into units containing combinational subcircuits, searches paths within those units, and outputs the analysis results.
Career Highlights
Tonooka’s patent reflects work on improving the efficiency and precision of circuit-timing analysis. The disclosed approach organizes the analysis into defined stages, from processing net-list data to reporting the resulting paths.
Collaborations
Tonooka’s listed coworkers include Junichi Tsujimoto and Mototaka Kuribayashi. His work is associated with Kabushiki Kaisha Toshiba.
Conclusion
Yasuhiro Tonooka’s patented method addresses key challenges in LSI static-timing analysis by seeking to reduce both false paths and processing time.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile