Hoya, Japan

Yasuhiro Horiike

This inventor holds 1 USPTO granted patent. Top assignee: Applied Materials, Inc.. Active years: 2002.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yasuhiro Horiike. Retrieved from https://idiyas.com/inventor/yasuhiro-horiike-42ev7kdr

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1

Forward Citations = 7(Granted Patents)


Company Filing History:


Years Active: 2002

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1 patent (USPTO):Explore Patents

Title: Yasuhiro Horiike: Inventor in Semiconductor Etching

Introduction

Yasuhiro Horiike is an inventor associated with Hoya, Japan, and Applied Materials, Inc. His patent work concerns plasma etching processes for semiconductor manufacturing. He is credited with 1 patent.

Latest Patents

Horiike’s listed patent, “Etchant for Silicon Oxide and Method,” describes a method for etching silicon oxide with high selectivity relative to both a photoresist mask and a silicon-containing substrate. The method exposes silicon oxide to plasma generated from an etch-gas precursor containing a fluorocarbon and an organic silane with at least one organic group. The patent states that adding a sufficient proportion of silane can markedly improve selectivity, enabling the etching of high-aspect-ratio, submicron openings.

Career Highlights

Horiike’s patent reflects work on improving precision in semiconductor fabrication. The described process aims to selectively remove silicon oxide while limiting etching of the mask and underlying silicon-containing material.

Collaborations

Yoshio Ishikawa and Keiji Horioka are identified as Horiike’s coworkers. The available information does not specify their roles in the patent or the nature of their collaboration.

Conclusion

Yasuhiro Horiike’s listed invention addresses selective silicon oxide etching, a process relevant to producing fine, high-aspect-ratio features in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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