Xu Chen

Title: Xu Chen and His Patent in Decoder Architecture.

Introduction

Xu Chen is an inventor associated with The Hong Kong Polytechnic University in Hong Kong, CN. His patent work includes a decoder architecture designed to support high-throughput processing of low-density parity-check convolutional codes.

Latest Patents

The listed patent, “High Throughput Decoder Architecture for Low-Density Parity-Check Convolutional Codes,” describes a decoder for partial-parallel decoding. It uses pipeline processors containing block processing units, check node processors, variable node processors, and RAM blocks for storing channel and edge messages. The processors connect their node processors directly to corresponding RAM blocks, with connections predefined according to the parity-check matrix of an unterminated time-varying periodic code. Chen is associated with 1 patent.

Career Highlights

Chen’s listed patent reflects work on hardware architecture for decoding error-correcting codes. The design organizes message processing and memory access across multiple pipeline processors to support high-throughput decoding.

Collaborations

The provided information names Yue Zhao and Chiu Wing Sham as Chen’s coworkers. It does not specify their roles in the patent or describe particular collaborative contributions.

Conclusion

Xu Chen’s listed invention focuses on a structured, memory-connected decoder architecture for low-density parity-check convolutional codes, and is associated with his work at The Hong Kong Polytechnic University.