San Jose, CA, United States of America

Xiaocheng He

This inventor holds 1 USPTO granted patent and 2 published patent applications and 1 EPO patent. Top assignee: Avago Technologies International Sales Pte. Limited. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Xiaocheng He. Retrieved from https://idiyas.com/inventor/xiaocheng-he

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 1 

% Patents Active = 100.0


Average Co-Inventor Count = 2.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Xiaocheng He and Convolution Hardware Acceleration.

Introduction

Xiaocheng He is an inventor based in San Jose, California. His patent work includes a design for accelerating convolution operations in hardware, a key computation used in machine learning and image processing.

Latest Patents

He is associated with 1 patent, titled “Convolution Hardware Accelerator.” The invention describes a device with multiplication and accumulation (MAC) cells, a feature processor circuit, and a weight processor circuit. The feature processor organizes input elements from different channels into extended feature units, while the weight processor similarly organizes kernel elements into extended weight units. These units are delivered to corresponding MAC cells, which multiply the feature and weight elements in parallel and output the sum of the products. This arrangement is designed to support efficient convolution processing.

Career Highlights

He is associated with Avago Technologies International Sales Pte. Limited. His patented work reflects a focus on hardware architecture for processing convolution workloads.

Collaborations

Brian Francis Schoner is identified as a coworker. The available information does not specify whether he collaborated with He on the patent.

Conclusion

Xiaocheng He’s “Convolution Hardware Accelerator” patent describes a parallel hardware approach to convolution, highlighting his contribution to computational processing technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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